Buffer descriptor structures for communication between decoder and display manager

ABSTRACT

A system, method, and apparatus for decoding and displaying images utilizing two processors and two memory units. The decode process receives images which are encoded according to a predetermined standard. Included with the encoded images are parameters which facilitate the decode and display processes. The decode process decodes the encoded images and the encoded parameters and stores each image in a separate image buffer, and each set of associated parameters in a buffer descriptor structure associated with the image buffer. The decode process is carried on by the first processor. The display process utilizes the parameters associated with the image to determine the appropriate display order for each image, and then display the image accordingly on a display device, based on the associated parameters. The first processor carries on the display of the image on the display device. The second processor determines the display order for the images. The second processor and the second memory can be off-chip.

RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 10/725,974, entitled “VIDEO DISPLAY AND DECODE UTILIZING OFF-CHIP PROCESSOR AND DRAM,” filed Dec. 02, 2003, the complete subject matter of which is hereby incorporated herein by reference in its entirety. This application also claims benefit of U.S. Provisional Application Ser. No. 60/516,490, entitled VIDEO DISPLAY AND DECODE UTILIZING OFF-CHIP PROCESSOR AND DRAM,” filed Oct. 31, 2003, the complete subject matter of which is hereby incorporated herein by reference in its entirety.

FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[Not Applicable]

MICROFICHE/COPYRIGHT REFERENCE

[Not Applicable]

BACKGROUND OF THE INVENTION

Video decoders decode a video bit-stream encoded according to a predetermined standard syntax, such as MPEG-2 or Advanced Video Compression (AVC). An encoder generating a compressed video bit-stream makes a number of choices for converting the video stream into a compressed video bit-stream that satisfies the quality of service and bit-rate requirements of a channel and media. However, decoders have limited choices while decoding the compressed bit stream. The decoder uses the decisions made by the encoder to decode and present pictures at the output screen with the correct frame rate at the correct times, and the correct spatial resolution.

Decoding can be partitioned into two processes—the decode process and the display process. The decode process parses through the incoming bit stream and decodes the bit stream to produce decoded images which contain raw pixel data. The display process displays the decoded images onto an output screen at the proper time and at the correct and appropriate spatial and temporal resolutions as indicated in the display parameters received with the stream.

The decoding and display processes are usually implemented as firmware in Synchronous Random Access Memory (SRAM) executed by a processor. The processor is often customized and proprietary, and embedded. This is advantageous because the decoding process and many parts of the displaying process are very hardware-dependent. A customized and proprietary processor alleviates many of the constraints imposed by an off-the-shelf processor. Additionally, the decoding process is computationally intense. The speed afforded by a customized proprietary processor executing instructions from SRAM is a tremendous advantage. The drawbacks of using a customized proprietary processor and SRAM are that the SRAM is expensive and occupies a large area in an integrated circuit. Additionally, the use of proprietary and customized processor complicates debugging. The software for selecting the appropriate frame for display has been found, empirically, to be one of the most error-prone processes. Debugging of firmware for a customized and proprietary processor is complicated because few debugging tools are likely to exist, as compared to an off-the-shelf processor.

Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of ordinary skill in the art through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.

BRIEF SUMMARY OF THE INVENTION

Presented herein are buffer descriptor structures for communication between a decoder and a display manager.

In one embodiment, there is presented a system for providing images for display. The system comprises memory, a first processor and a second processor. The memory stores parameters associated with the images. The first processor decodes the images and writes the parameters associated with the images to the memory. The second processor reads the parameters from the memory and determines an order for displaying the images based on the parameters.

In another embodiment, there is present a circuit for providing images for display. The circuit comprises memory. The memory stores a first plurality of instructions and a second plurality of instructions. The execution the first plurality of instructions by a first processor causes the first processor to decode said images and write parameters associated with the images in a buffer. The execution of the plurality of instructions by a second processor causes the second processor to read the parameters associated with the images from the buffer and determine an order for displaying the images based on the parameters.

These and other features and advantages of the present invention may be appreciated from a review of the following detailed description of the present invention, along with the accompanying figures in which like reference numerals refer to like parts throughout.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 a illustrates a block diagram of an exemplary Moving Picture Experts Group (MPEG) encoding process, in accordance with an embodiment of the present invention.

FIG. 1 b illustrates an exemplary interlaced frame, in accordance with an embodiment of the present invention.

FIG. 1 c illustrates an exemplary sequence of frames in display order, in accordance with an embodiment of the present invention.

FIG. 1 d illustrates an exemplary sequence of frames in decode order, in accordance with an embodiment of the present invention.

FIG. 2 illustrates a block diagram of an exemplary circuit for decoding the compressed video data, in accordance with an embodiment of the present invention.

FIG. 3 illustrates a block diagram of an exemplary decoder and display engine unit for decoding and displaying video data, in accordance with an embodiment of the present invention.

FIG. 4 a illustrates a dynamic random access memory (DRAM) unit 309, in accordance with an embodiment of the present invention.

FIG. 4 b illustrates an exemplary 3:2 pulldown technique, in accordance with an embodiment of the present invention.

FIG. 5 illustrates a timing diagram of the decoding and displaying process, in accordance with an embodiment of the present invention.

FIG. 6 illustrates a flow diagram describing a decode and display process, in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 a illustrates a block diagram of an exemplary Moving Picture Experts Group (MPEG) encoding process of video data 101, in accordance with an embodiment of the present invention. The video data 101 comprises a series of frames 103. Each frame 103 comprises two-dimensional grids of luminance Y, 105, chrominance red C_(r), 107, and chrominance blue C_(b), 109, pixels.

FIG. 1 b is an illustration of a frame 103. A frame 103 can either be captured as an interlaced frame or as a progressive frame. In an interlaced frame 103, the even-numbered lines are captured during one time interval, while the odd-numbered lines are captured during an adjacent time interval. The even-numbered lines form the top field, while the odd-numbered lines form the bottom field of the interlaced frame.

Similarly, a display device can display a frame in progressive format or in interlaced format. A progressive display displays the lines of a frame sequentially, while an interlaced display displays one field followed by the other field. In a special case, a progressive frame can be displayed on an interlaced display by displaying the even-numbered lines of the progressive frame followed by the odd-numbered lines, or vice versa.

Referring again to FIG. 1 a, the two-dimensional grids are divided into 8×8 blocks, where a group of four blocks or a 16×16 block 113 of luminance pixels Y is associated with a block 115 of chrominance red C_(r), and a block 117 of chrominance blue C_(b) pixels. The block 113 of luminance pixels Y, along with its corresponding block 115 of chrominance red pixels C_(r), and block 117 of chrominance blue pixels C_(b) form a data structure known as a macroblock 111. The macroblock 111 also includes additional parameters, including motion vectors, explained hereinafter. Each macroblock ill represents image data in a 16×16 block area of the image.

The data in the macroblocks 111 is compressed in accordance with algorithms that take advantage of temporal and spatial redundancies. For example, in a motion picture, neighboring frames 103 usually have many similarities. Motion causes an increase in the differences between frames, the difference being between corresponding pixels of the frames, which necessitate utilizing large values for the transformation from one frame to another. The differences between the frames may be reduced using motion compensation, such that the transformation from frame to frame is minimized. The idea of motion compensation is based on the fact that when an object moves across a screen, the object may appear in different positions in different frames, but the object itself does not change substantially in appearance, in the sense that the pixels comprising the object have very close values, if not the same, regardless of their position within the frame. Measuring and recording the motion as a vector can reduce the picture differences. The vector can be used during decoding to shift a macroblock 111 of one frame to the appropriate part of another frame, thus creating movement of the object. Hence, instead of encoding the new value for each pixel, a block of pixels can be grouped, and the motion vector, which determines the position of that block of pixels in another frame, is encoded.

Accordingly, most of the macroblocks 111 are compared to portions of other frames 103 (reference frames). When an appropriate (most similar, i.e. containing the same object(s)) portion of a reference frame 103 is found, the differences between the portion of the reference frame 103 and the macroblock 111 are encoded. The location of the portion in the reference frame 103 is recorded as a motion vector. The encoded difference and the motion vector form part of the data structure encoding the macroblock 111. In the MPEG-2 standard, the macroblocks 111 from one frame 103 (a predicted frame) are limited to prediction from portions of no more than two reference frames 103. It is noted that frames 103 used as a reference frame for a predicted frame 103 can be a predicted frame 103 from another reference frame 103.

The macroblocks 111 representing a frame are grouped into different slice groups 119. The slice group 119 includes the macroblocks 111, as well as additional parameters describing the slice group. Each of the slice groups 119 forming the frame form the data portion of a picture structure 121. The picture 121 includes the slice groups 119 as well as additional parameters that further define the picture 121.

I₀, B₁, B₂, P₃, B₄, B₅, and P₆, FIG. 1 c, are exemplary pictures representing frames. The arrows illustrate the temporal prediction dependence of each picture. For example, picture B₂ is dependent on reference pictures I₀, and P₃. Pictures coded using temporal redundancy with respect to exclusively earlier pictures of the video sequence are known as predicted pictures (or P-pictures), for example picture P₃ is coded using reference picture I₀. Pictures coded using temporal redundancy with respect to earlier and/or later pictures of the video sequence are known as bi-directional pictures (or B-pictures), for example, pictures B₁ is coded using pictures I₀ and P₃. Pictures not coded using temporal redundancy are known as I-pictures, for example I₀. In the MPEG-2 standard, I-pictures and P-pictures are also referred to as reference pictures.

The foregoing data dependency among the pictures requires decoding of certain pictures prior to others. Additionally, the use of later pictures as reference pictures for previous pictures requires that the later picture is decoded prior to the previous picture. As a result, the pictures cannot be decoded in temporal display order, i.e., the pictures may be decoded in a different order than the order in which they will be displayed on the screen. Accordingly, the pictures are transmitted in data dependent order, and the decoder reorders the pictures for presentation after decoding. I₀, P₃, B₁, B₂, P₆, B₄, B₅, FIG. 1 d, represent the pictures in data dependent and decoding order, different from the display order seen in FIG. 1 c.

Referring again to FIG. 1 a, the pictures are then grouped together as a group of pictures (GOP) 123. The GOP 123 also includes additional parameters further describing the GOP. Groups of pictures 123 are then stored, forming what is known as a video elementary stream (VES) 125. The VES 125 is then packetized to form a packetized elementary sequence. Each packet is then associated with a transport header, forming what are known as transport packets.

The transport packets can be multiplexed with other transport packets carrying other content, such as another video elementary stream 125 or an audio elementary stream. The multiplexed transport packets form what is known as a transport stream. The transport stream is transmitted over a communication medium for decoding and displaying.

FIG. 2 illustrates a block diagram of an exemplary circuit for decoding the compressed video data, in accordance with an embodiment of the present invention. Data is received and stored in a presentation buffer 203 within a Synchronous Dynamic Random Access Memory (SDRAM) 201. The data can be received from either a communication channel or from a local memory, such as, for example, a hard disc or a DVD.

The data output from the presentation buffer 203 is then passed to a data transport processor 205. The data transport processor 205 demultiplexes the transport stream into packetized elementary stream constituents, and passes the audio transport stream to an audio decoder 215 and the video transport stream to a video transport processor 207 and then to a MPEG video decoder 209. The audio data is then sent to the output blocks, and the video is sent to a display engine 211.

The display engine 211 scales the video picture, renders the graphics, and constructs the complete display. Once the display is ready to be presented, it is passed to a video encoder 213 where it is converted to analog video using an internal digital to analog converter (DAC). The digital audio is converted to analog in an audio digital to analog converter (DAC) 217.

The decoder 209 decodes at least one picture, I₀, B₁, B₂, P₃, B₄, B₅, P₆, . . . , during each frame display period, in the absence of Personal Video Recording (PVR) modes when live decoding is turned on. Due to the presence of the B-pictures, B₁, B₂, the decoder 209 decodes the pictures, I₀, B₁, B₂, P₃, B₄, B₅, P₆, . . . , in an order that is different from the display order. The decoder 209 decodes each of the reference pictures, e.g., I₀, P₃, prior to each picture that is predicted from the reference picture. For example, the decoder 209 decodes I₀, B₁, B₂, P₃, in the order, I₀, P₃, B₁, and B₂. After decoding I₀ and P₃, the decoder 209 applies the offsets and displacements stored in B₁ and B₂, to the decoded I₀ and P₃, to decode B₁ and B₂. In order to apply the offset contained in B₁ and B₂, to the decoded I₀ and P₃, the decoder 209 stores decoded I₀ and P₃ in memory known as frame buffers 219. The display engine 211, then displays the decoded images onto a display device, e.g. monitor, television screen, etc., at the proper time and at the correct spatial and temporal resolution.

Since the images are not decoded in the same order in which they are displayed, the display engine 211 lags behind the decoder 209 by a delay time. In some cases the delay time may be constant. Accordingly, the decoded images are buffered in frame buffers 219 so that the display engine 211 displays them at the appropriate time. Accomplishing a correct display time and order, the display engine 211 uses various parameters decoded by the decoder 209 and stored in the parameter buffer 221, also referred to as Buffer Descriptor Structure (BDS).

A conventional system may utilize one processor to implement the decoder 209 and display engine 211. The decoding and display process are usually implemented as firmware in SRAM executed by a processor. The processor is often customized and proprietary, and embedded. This is advantageous because the decoding process and many parts of the displaying process are very hardware-dependent. A customized and proprietary processor alleviates many of the constraints imposed by an off-the-shelf processor. Additionally, the decoding process is computationally intense. The speed afforded by a customized proprietary processor executing instructions from SRAM is a tremendous advantage. The drawbacks of using a customized proprietary processor and SRAM is that the SRAM is expensive and occupies a large area in an integrated circuit. Additionally, the use of proprietary and customized processor complicates debugging. The software for selecting the appropriate frame for display has been found, empirically, to be one of the most error-prone processes. Debugging of firmware for a customized and proprietary processor is complicated because few debugging tools are likely to exist, as compared to an off-the-shelf processor.

The functionality of the decoder and display unit can be divided into three functions. One of the functions can be decoding the frames, another function can be displaying the frames, and another function can be determining the order in which decoded frames are displayed. The function for determining the order in which decoded frames are displayed can be off-loaded from the customized proprietary processor and implemented as firmware in DRAM that is executed by a more generic, “off-the-shelf” processor, such as, but not limited to, a MIPS processor or a RISC processor. The foregoing is advantageous because by offloading the firmware for selecting the frame for display from the SRAM, less space on an integrated circuit is consumed. Additionally, empirically, the process for selecting the image for display has been found to consume the greatest amount of time for debugging. By implementing the foregoing as firmware executed by an “off-the-shelf” processor, more debugging tools are available. Accordingly, the amount of time for debugging can be reduced.

Referring now to FIG. 3, there is illustrated a block diagram of the decoder system in accordance with an embodiment of the present invention. The second processor 307 oversees the process of selecting a decoded frame from the DRAM 309 for display and notifies the first processor 305 of the selected frame. The second processor 307 executes code that is also stored in the DRAM 309. The second processor 307 may comprise an “off-the-shelf” processor, such as a MIPS or RISC processor. The DRAM 309 and the second processor 307 can be off-chip. The system comprises a first processor 305, a first memory unit (SRAM) 303, a second processor 307, and a second memory unit (DRAM) 309.

The first processor 305 oversees the process of decoding the frames of the video frames, and displaying the video images on a display device 311. Alternatively, displaying the video images on a display device can also be offloaded to the second processor. The first processor 305 may run code that may be stored in the SRAM 303. The first processor 305 and the SRAM 303 are on-chip devices, thus inaccessible by a user, which is ideal for ensuring that important, permanent, and proprietary code cannot be altered by a user. The first processor 305 decodes the frames and stores the decoded frames in the DRAM 309.

The process of decoding and display of the frames can be implemented as firmware executed by one processor while the process for selecting the appropriate frame for display can be implemented as firmware executed by another processor. Because the decoding and display processes are relatively hardware-dependent, the decoding and display processes can be executed in a customized and proprietary processor. The firmware for the decoding and display processes can be implemented in SRAM.

On the other hand, the process for selecting the frame for display can be implemented as firmware in DRAM that is executed by a more generic, “off-the-shelf” processor, such as, but not limited to, a MIPS processor or a RISC processor. The foregoing is advantageous because by offloading the firmware for selecting the frame for display from the SRAM, less space on an integrated circuit is consumed. Additionally, empirically, the process for selecting the image for display has been found to consume the greatest amount of time for debugging. By implementing the foregoing as firmware executed by an “off-the-shelf” processor, more debugging tools are available. Accordingly, the amount of time for debugging can be reduced.

FIG. 4 a illustrates a dynamic random access memory (DRAM) unit 309, in accordance with an embodiment of the present invention. The DRAM 309 may contain frame buffers 409, 411 and 413 and corresponding parameter buffers for the BDSs, 403, 405 and 407.

In one embodiment of the present invention, the video data is provided to the processor 305. The display device 311 sends a vertical synchronization (vsynch) signal every time it is finished displaying a frame. When a vsynch is sent, the processor 305 may decode the next frame in the decoding sequence, which may be different from the display sequence as explained hereinabove. Since the second processor is an “off-the-shelf” processor, real time responsiveness of the second processor cannot be guaranteed. To allow the second processor 307 more time to select the frame for display, it is preferable that the second processor 307 selects the frame for display at the next vsynch, responsive to the present vsynch. Accordingly, after the vsynch, the first processor 305 loads parameters for the next decoded frame into the BDS. The second processor 307 can determine the next frame for display, by examining the BDS for all of the frame buffers. This decision can be made prior to the decoding of the next decoded frame, thereby allowing the second processor 307 a window of almost one display period prior to the next vsynch for determining the frame for display, thereat. The decoded frame is then stored in the appropriate buffer.

The processor 307 notifies the processor 305 of the decision regarding which frame should be displayed next. When the display device 311 sends the next vsynch signal, the foregoing is repeated and the processor 305 displays the frame that was determined by processor 307 prior to the latest vsynch signal. The process of displaying the frame selected by the second processor prior to the latest vsynch may also be implemented utilizing the second processor. Consequently, the first processor may not need to interface with the display hardware and may work based only on the vsynchs and the signals for determining which frame to overwrite from the second processor. The processor 305 gets the frame to display and its BDS from the DRAM 309, applies the appropriate display parameters to the frame and sends it for display on the display device 311.

The frame buffers 409, 411, and 413 in the DRAM 309 may have limited storage space, therefore, when a new frame is sent from the first processor 305, if the frame buffer where the decoded frame will be stored contains data that is not required by the display process in the second processor and the data is not needed for any predictions, that older frame would be overwritten. In one embodiment of the present invention, there may be three frame buffers in the DRAM 309, corresponding to each of the three frame types, I, P and B pictures.

In MPEG-2 two I or P frames at a time, because two I or P frames (reference frames) are used to decode B frames. Accordingly, the two most recently decoded I or P frames are stored in two of the frame buffers. When a new I or P decoded frame is sent by the first processor 305 to be stored in the DRAM 309, the oldest I or P decoded frame may be overwritten.

When a B frame is decoded, the B frame stored in the frame buffer is overwritten. However, it is possible that while the decoded B frame is decoded, the B frame stored in the frame buffer is being displayed. This occurs when two consecutive B frames are displayed. Waiting to decode the B frame until after the entire B frame in the frame buffer has been displayed may not allow enough time to decode the new B frame before display time. Accordingly, the decode B frame is decoded in portions as portions of the display B frame are displayed. After a portion of the display B frame is displayed, a corresponding portion of the decode B frame is decoded and the displayed portion of the displayed B frame is overwritten with the decoded portion of the decode B frame. The foregoing can be done provided that the overwritten portion of the display B frame is no longer needed, i.e. is being displayed for the last time.

There are cases however, where a display B frame may be scanned again, such as, for example, when the 3:2 pulldown technique is utilized. Referring now to FIG. 4 b, there is illustrated a block diagram describing the display of frames using the 3:2 pulldown technique. The 3:2 pulldown technique is used to convert video data in the film mode standard frame rate for display in the NTSC (National Television System Committee) standard frame rate. Video data in the film mode standard frame rate comprises 24 progressive frames per second. An NTSC display, however, displays 30 interlaced frames per second, or 60 fields per second. The video data in the film mode standard is displayed on an NTSC display by displaying five fields for every two progressive frames. For one frame 127 the top field 131 is displayed, followed by the bottom field 132, then the top field 133 from the following frame 128 is displayed, followed by the second frame's bottom field 134, then the top field 133, as illustrated in FIG. 4 b. For the subsequent two frames, 129 and 130, the bottom field 135 of the frame 129 is displayed, followed by the top field 136 of frame 129, followed by the bottom field 137 of frame 130, followed by the top field 138 of frame 130, and followed by the bottom field 137, again. If the B frame is displayed for two field periods, then replacing the B frame in the frame buffer can start as soon as the second field frame starts displaying. However, if the B frame needs to be displayed for three field periods, the video decoder waits until till the field that is displayed first, is being displayed a second time to start overwriting the B frame in the frame buffer. Other examples where B frames are scanned more than once are associated with PVR.

FIG. 5 illustrates a timing diagram of the decoding and displaying process, in accordance with an embodiment of the present invention. Processor 307 may be an off-the-shelf generic processor, and it may be off-chip If the first processor 305 were the only processor in the system, the code would only be in SRAM 303, and the processor 305 would be able to process, i.e. decode an image and determine the next image to display during a short period after the vsynch, then display that image during the time before the next vsynch signal. However, that is not desirable in this system since, as mentioned hereinabove, utilizing only the on-chip processor 305 and the SRAM 303 may be more costly than utilizing a second processor 307 and a DRAM 309. The second processor 307 and the DRAM 309 may be more economical.

When the vsynch occurs, the processor 307 determines the appropriate image to display next according to the correct order. It is desirable to provide processor 307 with the necessary information to determine the next frame for display early, to afford the processor 307 more time to determine the next frame for display. As a result, when, for instance, a vsynch 0 occurs, processor 305 and processor 307 are notified. Processor 305 then depending on the next frame to decode does different things. If the next frame to decode is an I or a P frame, processor 305 may load the BDS information associated with the frame that is being currently decoded onto the DRAM 309 and notify the processor 307. The processor 307 determines the appropriate frame to display next to maintain the correct order of frames based on the BDS. Meanwhile, the processor 305 also begins displaying the current display frame, e.g. frame 0, and decoding the current decode frame utilizing instructions stored on the SRAM 303. Once the decoding of the current frame is complete, the processor 305 may send the decoded frame to the DRAM 309, and overwrites the oldest I or P frame in the appropriate frame buffer. Processor 305 may overwrite frames in DRAM while the decoding is in progress.

If, however, the next frame to be decoded is a B frame, processor 305 sends a signal to processor 307. The processor 307 then determines whether a B frame is being displayed for the last time, and sends a signal to processor 305. When processor 305 receives the signal that a B frame is being displayed for the last time, processor 305 may load the BDS information associated with the B frame that is being currently decoded onto the DRAM 309. As the B frame is being displayed for the last time, the processor 305 decodes the next B frame and overwrites the B frame that is being currently displayed, as it is being displayed.

Once the processor 307 determines, for instance, frame 1 that needs to be displayed next, processor 307 sends the determination information to processor 305. At vsynch 1, the foregoing is repeated and processor 305 displays the frame selected after vsynch 0, e.g. frame 1, from the DRAM 309.

The embodiments described herein may be implemented as a board level product, as a single chip, application-specific integrated circuit (ASIC), or with varying levels of the decoder system integrated with other portions of the system as separate components. The degree of integration of the decoder system will primarily be determined by the speed and cost considerations. Because of the sophisticated nature of modern processors, it is possible to utilize a commercially available processor, which may be implemented external to an ASIC implementation. Alternatively, if the processor is available as an ASIC core or logic block, then the commercially available processor can be implemented as part of an ASIC device wherein certain functions can be implemented in firmware.

While the present invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from its scope. Therefore, it is intended that the present invention not be limited to the particular embodiment disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims. 

1. A system for providing images for display, said system comprising: memory for storing parameters associated with the images; a first processor for decoding said images and writing said parameters associated with the images to the memory; a second processor for reading the parameters from the memory and determining an order for displaying the images based on the parameters.
 2. The system of claim 1, wherein the memory stores the decoded images.
 3. The system of claim 2 wherein the second processor determines times to overwrite particular ones of the decoded images in the memory based on the parameters.
 4. The system of claim 3, wherein the first processor overwrites the particular ones of the decoded images in the memory.
 5. The system of claim 4, wherein the second processor signals the first processor to overwrite the particular ones of the decoded images at approximately said times, and wherein the first processor overwrites the particular ones of the decoded images after the second processor signals the first processor.
 6. The system of claim 1, wherein the parameters comprises a parameter from a group parameters consisting of repeat first field and top field first.
 7. The system of claim 1, wherein the first processor provides the images for display according to the order determined by the second processor.
 8. A circuit for providing images for display, said circuit comprising: memory for storing: a first plurality of instructions, the execution the first plurality of instructions by a first processor causing the first processor to decode said images and write parameters associated with the images in a buffer; and a second plurality of instructions, the execution of the plurality of instructions by a second processor causing the second processor to read the parameters associated with the images from the buffer and determine an order for displaying the images based on the parameters.
 9. The circuit of claim 8, wherein execution of the first plurality of instructions by the first processor causes the first processor to write the decoded images in the buffer.
 10. The circuit of claim 9 wherein execution of the second plurality of instructions by the second processor causes the second processor to determine times to overwrite particular ones of the decoded images in the memory based on the parameters.
 11. The circuit of claim 10, wherein execution of the first plurality of instructions by the first processor causes the first processor to overwrite the particular ones of the decoded images in the buffer.
 12. The circuit of claim 11, wherein execution of the second plurality of instructions by the second processor causes the second processor to signal the first processor to overwrite the particular ones of the decoded images at approximately said times, and wherein execution of the first plurality of instructions by the first processor cause the first processor to overwrite the particular ones of the decoded images after the second processor signals the first processor.
 13. The circuit of claim 8, wherein the parameters comprises a parameter from a group parameters consisting of repeat first field, and top field first.
 14. The circuit of claim 8, wherein execution of the first plurality of instructions by the first processor causes the first processor to provide the images for display according to the order determined by the second processor. 